In integrated circuit (IC) chip designs, signals (e.g., clock signals, logic signals, power signals, etc.) may propagate along “long” metal wires in comparison to minimum design sizes available in the fabrication process utilized. Propagation delay and distortion are some of the negative effects experienced by the signals propagating along the long metal wires. These negative effects can be minimized by reducing the RC constant of the metal wire. However, in some IC chip designs, the maximum reduction in the RC constant is not sufficient to meet the design specifications. Thus, other techniques are used. One approach involves inserting repeater circuits at periodic intervals along the long metal wires in order to amplify (or remove distortion) the signals as well as to reduce propagation delay (or maintain fast transition times). However, conventional repeaters introduce a propagation delay as a result of one or more parasitic capacitances.